The present invention relates to a semiconductor device, more particularly, to a semiconductor device and a method thereof, in which a capacitor included in a unit cell of the semiconductor device is formed between gate patterns so that manufacturing time and cost as well as a defect ratio of manufactured products are reduced.
A semiconductor device functioning as an electronic apparatus designed to perform a specific operation can be fabricated using a process including steps of injecting an impure material and depositing conductive and nonconductive materials onto a predetermined area of a wafer mounted in chamber. For example, a semiconductor memory device is an example of a semiconductor device that can be made by such a process. A semiconductor memory device can include various components or elements such as a transistor, a capacitor, a resistor, a fuse, and others. In an exemplary semiconductor memory, a capacitor is often mainly used for temporarily storing data, and a fuse can be used in a redundancy circuit and/or in a power supply circuit of the semiconductor memory. Various elements in a semiconductor memory device are generally connected to one another through a conductive layer to transmit data, control signals and/or other information among the elements.
Manufacturing technology for semiconductor devices has advanced to allow an increased integration density in devices, and a corresponding decrease in the size of chips. Hence a wafer can include more chips than that in the past. When increasing the density, the minimum line width specified by a design rule is generally decreased. Another consequence of greater integration density is that the semiconductor devices can operate at greater speeds while consuming less power.
A semiconductor memory device generally includes a plurality of unit cells, each unit cell comprising a transistor and a capacitor. When an electrical signal representing a binary data value of “1” is delivered to a capacitor, an amount of electric charge is temporarily stored in a storage node SN connected to one electrode of the capacitor. However, the amount of electric charge retained in the capacitor decreases over time owing to leakage current at a junction of the storage node, and/or other capacitor leakage characteristics. In an effort to ameliorate leakage, the capacitance Cs of the capacitor in the unit cell may be increased so that the semiconductor memory device can store a greater amount of electric charge in the storage node SN during a write operation. One of the most common approaches to increasing the capacitance Cs of the capacitor is to replace at least a portion of the oxide dielectric layer found in the storage node of conventional unit cells with an insulator having a higher dielectric constant than oxide, such as a nitrided oxide layer. Furthermore, if the substitute dielectric has superior insulating properties, the junction leakage current may be reduced. Yet another method to increase the capacitance Cs of the capacitor is to form the capacitor in a three-dimensional structure such as a cylindrical structure or a trench structure, thereby providing increased capacitor electrode area relative to a conventional two-dimensional planar structure.
When design rule dimensions are reduced, the allowable planar cross sectional area in which a capacitor can be formed is also reduced. To at least partly compensate for the decrease in distance between adjacent gate patterns with smaller design rules, it is common for a capacitor connected to source/drain between adjacent gate patterns to be formed in a configuration that situates at least a portion of the capacitor in an upper level of the device above the gate pattern or the bit line, rather than being confined entirely within the two dimensional space bounded by the gate patterns.
FIG. 1 is a cross-sectional view showing aspects of a conventional semiconductor device.
As illustrated in FIG. 1, the semiconductor device includes an active region 104 defined by a field isolation layer 102 which is formed over a semiconductor substrate using conventional shallow trench isolation (STI) techniques. Gate patterns 106a and 106b are formed on the field isolation layer 102 and the active region 104. Also, although not shown in the drawing, a source/drain region is formed on both sides of the gate pattern 106a. 
Landing plug contacts 108a and 108b are formed on the source/drain region that is positioned between adjacent gate patterns. The landing plug contact 108a formed between adjacent gate patterns 106a that are formed on the active region 104 is connected to a bit line contact 112 and a bit line 110. The landing plug contact 108b formed between the gate pattern 106a, which is formed on the active region 104, and the gate pattern 106b, which is formed on the field isolation layer 102, is connected to a capacitor 120.
The gate patterns 106a and 106b as part of a word line intersect the bit line 110 and, as shown in FIG. 1. The bit line 110 is positioned to be higher than the gate patterns 106 and 106b. 
The capacitor 120 must be electrically insulated from the bit line 110 and, as mentioned above, preferably has a large capacitance. Thus, the capacitor 120 is in a position above the bit line 110 and has a high aspect ratio pillar shape that extends in a vertical direction. A storage node contact 114 to the capacitor is additionally formed in the semiconductor memory device for connecting the capacitor 120 to the landing plug contact 108b that is formed between the gate patterns 106a and 106b. 
A plate line 122 for transferring a plate voltage to one electrode of the capacitor 120 is formed on the capacitor 120. Metal interconnections and fuses M1 through M3 are formed on the plate line 122. Although not described herein, various insulation layers can be formed between various components of the semiconductor device where electrical connection is unwanted.
The structure of the semiconductor memory device illustrated in FIG. 1 is designed to maintain the capacitance of the capacitor as design rules are decreased, and allows forming the capacitor in a high aspect ratio pillar pattern in a position above the bit line 110. In this manner, the capacitor can have increased surface area by forming a capacitor having the greatest practical height in a given horizontal cross sectional planar surface area. Such a pillar shaped capacitor pattern can nearly double capacitance relative to a two dimensional planar structure. However because this type of pillar pattern capacitor tends to incline from vertical owing to the high aspect ratio and because patterns formed in the central area and peripheral areas of a wafer often have different thicknesses or sizes, it is difficult to manufacture a cell array of such capacitors having sufficiently uniform characteristics.
In addition, metal interconnections and the fuses formed over the capacitor are elements that are to be formed at a later processing step. It is difficult to control the thickness and/or the size of the metal interconnection and the fuse because the metal interconnection and the fuse are formed by a process of depositing and patterning metal on the isolation layer while simultaneously ensuring that no damage occurs to other components such as the capacitor that are in a position below the metal interconnection and fuse levels.